The present invention relates to a phase change random access memory, referred to as PRAM hereinafter, and, more particularly, to a technology for implementing a function of evaluating the lifetime and reliability of a cell in a write driver circuit of the PRAM.
Recently, a phase change random access memory (PRAM) is drawing attention as a next generation semiconductor memory and is implemented using a phase change material.
The PRAM includes a cell storing data by using a germanium antimony telluride (Ge2Sb2Te5), referred to as GST hereinafter, which is one of phase change materials. The GST as a phase change material changes to crystalline or amorphous state according to the change of temperature and the amount of current, and the PRAM stores data “0” or “1” according to the phase change.
Upon a write operation, when a current flows on the GST, the GST changes to the crystalline or amorphous state. The phase change of the GST occurs due to the Joule heating generated by a current applied to a cell.
Upon the write operation, when the GST is heated to above its melting temperature by a write current IWRITE and then is rapidly cooled, the phase of the GST changes to the amorphous state, and stores data “H” corresponding to the phase change. The amorphous state is referred to as a reset state.
Upon the write operation, when the GST is heated to above the crystallization temperature by the write current IWRITE and then is cooled after being maintained for a certain period, the phase of the GST changes to the crystalline state and stores data “L” corresponding to the phase change. The crystalline state is referred to as a set state.
FIG. 1 illustrates a typical write driver 10 of a PRAM.
The write driver 10 includes a set current source SET, a reset current source RESET, and a plurality of PMOS transistors M0, M1 and M2 controlling a write current IWRITE.
Due to the reset current source RESET, when the write current IWRITE flows through the PMOS transistor M2 in proportion to a current flowing through the reset current source RESET, a GST cell (not shown) connected to a bit line (not shown) changes to the reset state, and accordingly the PRAM stores data “H” corresponding to the reset state of the GST cell.
Due to the set current source SET, when the write current IWRITE flows through the PMOS transistor M2 in proportion to a current flowing through the set current source SET, the GST cell connected to the bit line changes to the set state, and accordingly the PRAM stores data “L” corresponding to the set state of the GST cell.
As described above, the reliability of the PRAM storing data depends on the life cycle and reliability of the GST cell. Therefore, in order to secure the reliability of the PRAM, it is necessary to evaluate the life cycle and reliability of the GST cell supplied with a write current as described above with reference to FIG. 1.
Accordingly, in order to evaluate the life cycle and reliability of the GST cell, an appropriate method of evaluating the life cycle and reliability of the GST cell by giving a stress during a short period under a severe environment such as burn-in condition is required.